selected scholarly activity
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books
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chapters
- On-Chip Constrained-Random Stimuli Generation. 125-144. 2019
- Selection of Post-Silicon Hardware Assertions. 179-208. 2019
- Improving compression ratio, area overhead, and test application time for system-on-chip test data compression/decompression. 479-495. 2008
- Approaches to Handle Test Power. 31-49.
- Design and Test of Digital Integrated Circuits. 1-20.
- Power Dissipation During Test. 21-30.
- Power Minimization Based on Best Primary Input Change Time. 51-85.
- Power-conscious Test Synthesis and Scheduling. 113-137.
- Test Power Minimization Using Multiple Scan Chains. 87-112.
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conferences
- An automated SAT-based method for the design of on-chip bit-flip detectors. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. 101-108. 2017
- A generic embedded sequence generator for constrained-random validation with weighted distributions. 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS). 57-62. 2017
- Message from the general chair. 2017 IEEE North Atlantic Test Workshop (NATW). 1-4. 2017
- An Automated SAT-based Method for the Design of On-Chip Bit-flip Detectors. 2017 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD). 101-108. 2017
- Bit-flip detection-driven selection of trace signals. Proceedings of the European Test Workshop. 1-6. 2016
- Message from General and Program Chairs. 2016 IEEE 25th North Atlantic Test Workshop (NATW). vii. 2016
- Bit-flip Detection-Driven Selection of Trace Signals. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016
- On-chip generation of uniformly distributed constrained-random stimuli for post-silicon validation. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design. 808-815. 2015
- SAT solving using FPGA-based heterogeneous computing. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design. 232-239. 2015
- Emulation-based selection and assessment of assertion checkers for post-silicon validation. 2015 33rd IEEE International Conference on Computer Design (ICCD). 46-53. 2015
- Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug. 2015 IEEE 24th North Atlantic Test Workshop. 17-22. 2015
- A Methodology for Automated Design of Embedded Bit-flips Detectors in Post-Silicon Validation. Proceedings -Design, Automation and Test in Europe, DATE. 73-78. 2015
- On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli. Proceedings of the Asian Test Symposium. 107-112. 2014
- On-chip constrained random stimuli generation for post-silicon validation using compact masks. IEEE International Test Conference (TC). 2014
- FPGA acceleration of enhanced boolean constraint propagation for SAT solvers. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. 234-241. 2013
- Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation. Proceedings - Design Automation Conference. 1-6. 2013
- In-system constrained-random stimuli generation for post-silicon validation. IEEE International Test Conference (TC). 2012
- On-chip stimuli generation for post-silicon validation. Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT. 108-109. 2012
- Tutorials. 2012 IEEE 21st Asian Test Symposium. xviii-xix. 2012
- Automated data analysis techniques for a modern silicon debug environment. 17th Asia and South Pacific Design Automation Conference. 298-303. 2012
- In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. 434-441. 2011
- A New Algorithm for Post-Silicon Clock Measurement and Tuning. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 53-59. 2011
- Dynamic binary translation to a reconfigurable target for on-the-fly acceleration. Proceedings - Design Automation Conference. 286-287. 2011
- Automated trace signals selection using the RTL descriptions. IEEE International Test Conference (TC). 2010
- Combined optimal and heuristic approaches for multiple constant multiplication. IEEE International Conference on Computer Design - VLSI in Computers and Processors. 266-273. 2010
- A novel optimal single constant multiplication algorithm. Proceedings - Design Automation Conference. 613-616. 2010
- Embedded memory binding in FPGAs. Proceedings - Design Automation Conference. 457-462. 2010
- Post-silicon validation opportunities, challenges and recent advances. Proceedings - Design Automation Conference. 12-17. 2010
- Robust design methods for hardware accelerators for iterative algorithms in scientific computing. Proceedings - Design Automation Conference. 254-257. 2010
- Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. 2010 15th IEEE European Test Symposium. 62-67. 2010
- Automated silicon debug data analysis techniques for a hardware data acquisition environment. Proceedings - International Symposium on Quality Electronic Design, ISQED. 675-682. 2010
- Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture. Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays. 189-197. 2010
- Design-for-debug for post-silicon validation: Can high-level descriptions help?. Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT. 172-175. 2009
- Computational bit-width allocation for operations in vector calculus. IEEE International Conference on Computer Design - VLSI in Computers and Processors. 433-438. 2009
- A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications. Proceedings of the Custom Integrated Circuits Conference. 499-+. 2009
- Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. Proceedings of the European Test Workshop. 17-22. 2009
- Automated data analysis solutions to silicon debug. Proceedings -Design, Automation and Test in Europe, DATE. 982-+. 2009
- Finite Precision bit-width allocation using SAT-Modulo Theory. Proceedings -Design, Automation and Test in Europe, DATE. 1106-1111. 2009
- An energy-efficient architecture for MPEG-2 audio/video decoding. 2008 1st Microsystems and Nanoelectronics Research Conference. 149-152. 2008
- Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs. IEEE International Test Conference (TC). 422-431. 2008
- Hardware-based parallel computing for real-time haptic rendering of deformable objects. 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems. 4187-4187. 2008
- On Bypassing Blocking Bugs during Post-Silicon Validation. Proceedings of the European Test Workshop. 69-74. 2008
- Automated trace signals identification and state restoration for improving observability in post-silicon validation. Proceedings of the conference on Design, automation and test in Europe. 1298-1303. 2008
- On Automated Trigger Event Generation in Post-Silicon Validation.. Proceedings of the conference on Design, automation and test in Europe. 256-259. 2008
- A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. 9th International Symposium on Quality Electronic Design (isqed 2008). 649-654. 2008
- Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. Proceedings -Design, Automation and Test in Europe, DATE. 1298-1303. 2008
- Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing. 9th International Symposium on Quality Electronic Design (isqed 2008). 832-837. 2008
- On Automated Trigger Event Generation in Post-Silicon Validation. Proceedings -Design, Automation and Test in Europe, DATE. 256-259. 2008
- Power-Aware Testing and Test Strategies for Low Power Devices. 2008 Design, Automation and Test in Europe. xliv-xliv. 2008
- A novel automated scan chain division method for shift and capture power reduction in broadside at-speed test. ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN. 649-654. 2008
- Automated trace signals identification and state restoration for improving observability in post-silicon validation. Proceedings -Design, Automation and Test in Europe, DATE. 1140-1145. 2008
- Embedded deterministic test exploiting care bit clustering and seed borrowing. ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN. 832-837. 2008
- IP Session 4C: Bridging Pre-Silicon Verification and Post-Silicon Validation and Debug. 26th IEEE VLSI Test Symposium (vts 2008). 155. 2008
- Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-Chip Test Data Compression/Decompression. 604-611. 2008
- On automated trigger event generation in post-silicon validation. Proceedings -Design, Automation and Test in Europe, DATE. 1328-1331. 2008
- DATE 07 workshop on diagnostic services in NoCs. IEEE Design and Test. 510-510. 2007
- Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 1539-1547. 2007
- Embedded Tutorial on Low Power Test. Proceedings of the European Test Workshop. 202-+. 2007
- Low Cost Debug Architecture using Lossy Compression for Silicon Debug. Proceedings -Design, Automation and Test in Europe, DATE. 225-230. 2007
- On using lossless compression of debug data in embedded logic analysis. IEEE International Test Conference (TC). 495-504. 2007
- On using lossless compression of debug data in embedded logic analysis. 2007 IEEE International Test Conference. 1-10. 2007
- Session Abstract. 25th IEEE VLSI Test Symposium (VTS'07). 477-478. 2007
- RTL Scan Design for Skewed-Load At-Speed Test under Power Constraints. IEEE International Conference on Computer Design - VLSI in Computers and Processors. 237-242. 2006
- Multifrequency TAM design for hierarchical SOCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 181-196. 2006
- Modular SOC testing with reduced wrapper count. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 1894-1908. 2005
- On concurrent test of wrapped cores and unwrapped logic blocks in SOCs. IEEE International Test Conference (TC). 600-609. 2005
- Multi-frequency wrapper design and optimization for embedded cores under average power constraints. Proceedings - Design Automation Conference. 123-128. 2005
- Multi-frequency wrapper design and optimization for embedded cores under average power constraints. Proceedings of the 42nd annual conference on Design automation - DAC '05. 123-128. 2005
- Register-transfer level functional scan for hierarchical designs. Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05. 1172-1175. 2005
- Register-transfer level functional scan for hierarchical designs. Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.. 1172-1175. 2005
- Time-Multiplexed Test Data Decompression Architecture for Core-Based SoCs with Improved Utilization of Tester Channels. European Test Symposium (ETS'05). 196-201. 2005
- Compressed embedded diagnosis of logic cores. IEEE International Conference on Computer Design - VLSI in Computers and Processors. 534-539. 2004
- Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. Proceedings of the Asian Test Symposium. 454-459. 2004
- Functional illinois scan design at RTL. IEEE International Conference on Computer Design - VLSI in Computers and Processors. 78-81. 2004
- Multi-Frequency Test Access Mechanism Design for Modular SOC Testing. Proceedings of the Asian Test Symposium. 2-7. 2004
- Time/area tradeoffs in testing hierarchical SOCs with hard mega-cores. IEEE International Test Conference (TC). 1196-1202. 2004
- Wrapper design for testing IP cores with multiple clock domains. Proceedings Design, Automation and Test in Europe Conference and Exhibition. 1-6. 2004
- Wrapper design for testing TP cores with multiple clock domains. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS. 416-421. 2004
- Variable-length input huffman coding for system-on-a-chip test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 783-796. 2003
- Delay fault testing of core-based systems-on-a-chip. Proceedings -Design, Automation and Test in Europe, DATE. 744-749. 2003
- Embedded compact deterministic test for IP-protected cores. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 519-526. 2003
- Embedded compact deterministic test for IP-protected cores. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 519-526. 2003
- Hardware/software co-testing of embedded memories in complex SOCs. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. 599-605. 2003
- On reducing wrapper boundary register cells in modular soc testing. IEEE International Test Conference (TC). 622-631. 2003
- Power-constrained embedded memory BIST architecture. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 451-458. 2003
- Power-constrained embedded memory BIST architecture. Proceedings. 16th IEEE Symposium on Computer Arithmetic. 451-458. 2003
- Test data compression: the system integrator's perspective. Proceedings -Design, Automation and Test in Europe, DATE. 726-731. 2003
- Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression. Proceedings -Design, Automation and Test in Europe, DATE. 604-611. 2002
- Integrated test data decompression and core wrapper design for low-cost system-on-a-chip testing. IEEE International Test Conference (TC). 64-73. 2002
- Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding. IEEE International Conference on Computer Design - VLSI in Computers and Processors. 474-479. 2002
- Scan architecture for shift and capture cycle power reduction. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 129-137. 2002
- Useless memory allocation in system-on-a-chip test: problems and solutions. Proceedings 20th IEEE VLSI Test Symposium (VTS 2002). 423-429. 2002
- Power constrained test scheduling using power profile manipulation. ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. 251-254. 2001
- Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation. IEEE International Test Conference (TC). 72-81. 2001
- Testability trade-offs for BIST RTL data paths: the case for three dimensional design space. Proceedings -Design, Automation and Test in Europe, DATE. 802-802. 2001
- Power conscious test synthesis and scheduling for BIST RTL data paths. IEEE International Test Conference (TC). 662-671. 2000
- Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. Proceedings -Design, Automation and Test in Europe, DATE. 715-722. 2000
- Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits. Proceedings of the conference on Design, automation and test in Europe. 715-722. 2000
- Efficient BIST hardware insertion with low test application time for synthesized data paths. Proceedings -Design, Automation and Test in Europe, DATE. 289-295. 1999
- Interactive presentation: Low cost debug architecture using lossy compression for silicon debug.. 225-230.
- Useless Memory Allocation: Problems and Solutions
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journal articles
- Fast Inner-Product Algorithms and Architectures for Deep Neural Network Accelerators. IEEE transactions on computers. 73:495-509. 2024
- Interview With Prof. Sung-Mo (Steve) Kang. IEEE Design and Test. 40:64-67. 2023
- Interview With Janet Olson. IEEE Design and Test. 40:112-115. 2023
- Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:750-763. 2020
- Bit-Flip Detection-Driven Selection of Trace Signals. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37:1076-1089. 2018
- Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:1866-1880. 2017
- Guest Editors' Introduction: Top Papers from the 2015 International Test Conference. IEEE Design and Test. 33:5-6. 2016
- On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35:1012-1025. 2016
- Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35:2118-2130. 2016
- Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation. IEEE transactions on computers. 65:1-1. 2016
- A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation. Transactions on Embedded Computing Systems. 13:1-23. 2014
- A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning. IEEE transactions on computers. 63:1074-1084. 2014
- Guest Editors' Introduction: Silicon Debug and Diagnosis. IEEE Design and Test. 30:6-7. 2013
- NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging. IEEE transactions on computers. 62:524-535. 2013
- On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31:1845-1856. 2012
- Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging. IEEE transactions on computers. 61:1563-1575. 2012
- Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:1118-1131. 2012
- Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types. IEEE transactions on computers. 60:1652-1663. 2011
- An Optimal and Practical Approach to Single Constant Multiplication. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30:1373-1386. 2011
- Automated Range and Precision Bit-Width Allocation for Iterative Computations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30:1265-1278. 2011
- Design-for-Debug Architecture for Distributed Embedded Logic Analysis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19:1380-1393. 2011
- Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research. IEEE Design and Test. 28:6-7. 2011
- Numerical Data Representations for FPGA-Based Scientific Computing. IEEE Design and Test. 28:8-17. 2011
- On Using Lossy Compression for Repeatable Experiments during Silicon Debug. IEEE transactions on computers. 60:937-950. 2011
- Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19:559-570. 2011
- Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses. IEEE transactions on computers. 60:498-507. 2011
- A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19:499-503. 2011
- Time-Multiplexed Compressed Test of SOC Designs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:1159-1172. 2010
- A Parallel Computing Platform for Real-Time Haptic Interaction with Deformable Bodies. IEEE Transactions on Haptics. 3:211-223. 2010
- Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29:405-413. 2010
- On improving real-time observability for in-system post-silicon debug. 2010 11th Latin American Test Workshop. 1-1. 2010
- Real-Time Lossless Compression for Silicon Debug. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28:1387-1400. 2009
- Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17:1353-1357. 2009
- Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28:285-297. 2009
- Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28:285-297. 2009
- Real-time lossless compression for silicon debug. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28:1387-1400. 2009
- Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27:2092-2097. 2008
- Guest Editorial. Journal of Electronic Testing: Theory and Applications (JETTA). 24:325-326. 2008
- Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. Journal of Electronic Testing: Theory and Applications (JETTA). 24:393-403. 2008
- Editorial: Silicon debug and diagnosis. IEE Proceedings: Computers and Digital Techniques. 1:659-659. 2007
- Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14:537-548. 2006
- DFT infrastructure for broadside two-pattern test of core-based SOCs. IEEE transactions on computers. 55:470-485. 2006
- Modular and rapid testing of SOCs with unwrapped logic blocks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13:1275-1285. 2005
- Wrapper design for multifrequency IP cores. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13:678-685. 2005
- Resource-constrained system-on-a-chip test: a survey. IEE Proceedings: Computers and Digital Techniques. 152:67-67. 2005
- Synchronization overhead in SOC compressed test. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13:140-152. 2005
- Scan Architecture With Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23:1142-1153. 2004
- Testability Trade-Offs for BIST Data Paths. Journal of Electronic Testing: Theory and Applications (JETTA). 20:169-179. 2004
- Power-Constrained Testing of VLSI Circuits 2004
- Addressing useless test data in core-based system-on-a-chip test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22:1568-1580. 2003
- Power-conscious test synthesis and scheduling. IEEE Design and Test. 20:48-55. 2003
- Test cost reduction through compression. IEE Electronics Systems and Software. 1:37-41. 2003
- Dual multiple-polynomial LFSR for low-power mixed-mode BIST. IEE Proceedings: Computers and Digital Techniques. 150:209-209. 2003
- Power profile manipulation: a new approach for reducing test application time under power constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21:1217-1225. 2002
- Multiple scan chains for power minimization during test application in sequential circuits. IEEE transactions on computers. 51:721-734. 2002
- Analysing trade-offs in scan power and test data compression for systems-on-a-chip. IEE Proceedings: Computers and Digital Techniques. 149:188-188. 2002
- Minimising power dissipation in partial scan sequential circuits. IEE Proceedings: Computers and Digital Techniques. 148:163-166. 2001
- Power constrained test scheduling using power profile manipulation. IEE Colloquium (Digest). 42:39-42. 2001
- Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip. Electronics Letters. 37:1434-1434. 2001
- BIST hardware synthesis for RTL data paths based on test compatibility classes. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 19:13751385. 2000
- BIST hardware synthesis for RTL data paths based on test compatibility classes. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 19:1375-1385. 2000
- Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing. IEE Proceedings: Computers and Digital Techniques. 147:313-313. 2000
- Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths. Proceedings of the conference on Design, automation and test in Europe. 60. 1999
- Correction to The Proof Of Theorem 2 In "parallel Signature Analysis Design With Bounds On Allasing". IEEE transactions on computers. 47:1426-1426. 1998
- [A rare cause of postoperative digestive hemorrhage].. Chirurgia (Romania). 93:421-422. 1998
- Low Power Testing of Digital ICs: Overview
- Low power test compatibility classes: Exploiting regularity for simultaneous reduction in test application time and power dissipation
- Power Constrained Test Scheduling Using Power Profile Manipulation, ISCAS 2001
- Power Minimisation Techniques for Testing Low Power VLSI Circuits
- Reducing Synchronization Overhead in Test Data Compression Environments
- Test Data Compression: The System Integrator?s Perspective. 2008 Design, Automation and Test in Europe. 1:10726-10726.
- Tutorial intitulé "Power-Aware Testing and Test Strategies for Low Power Devices"
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preprints