Conference
Functional Illinois Scan Design at RTL
Abstract
This paper shows that by creating functional scan chains at the register-transfer level (RTL), not only the timing of the circuit can be improved, but also the test data compression provided from the Illinois scan architecture is similar or even better than the gate level counterpart.
Authors
Ko HF; Nicolici N
Pagination
pp. 78-81
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
January 1, 2004
DOI
10.1109/iccd.2004.1347903
Name of conference
IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.