Journal article
Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation
Abstract
Once a bug is found during post-silicon validation, before committing to a silicon respin of the design it is expected that any other bugs, which have escaped pre-silicon verification, to be also identified. This will minimize the number of respins, which in turn will reduce the implementation costs. However, this is hindered by the presence of blocking bugs in one erroneous module that inhibit the search for bugs in other parts of the chip …
Authors
Daoud EA; Nicolici N
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 4, pp. 559–570
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
April 1, 2011
DOI
10.1109/tvlsi.2009.2038390
ISSN
1063-8210