IP Session 4C: Bridging Pre-Silicon Verification and Post-Silicon Validation and Debug

In this session, we discuss how to bridge the pre-silicon verification to post-silicon validation and debug. Can test patterns and test benches developed for verification be reused during validation? Can bugs identified in validation be confirmed again in the verification environment? How can the DfT infrastructure available on-chip for manufacturing test help with bridging pre-silicon verification and post-silicon validation and debug? Are the scan chains sufficient or do we need more on-chip support? Are there any other established test technologies that can aid the post-silicon validation process?