Estimating Word Lengths for Fixed-Point DSP Implementations Using Polynomial Chaos Expansions

Efficient custom hardware motivates the use of fixed-point arithmetic in the implementation of digital signal-processing (DSP) algorithms. This conversion to finite precision arithmetic introduces quantization noise in the system, which affects the system’s performance. As a result, characterizing quantization noise and its effects within a DSP system is a challenge that must be addressed to avoid over-allocating hardware resources during implementation. Polynomial chaos expansion (PCE) is a method used to model uncertainty in engineering systems. Although it has been employed to analyze quantization effects in DSP systems, previous investigations have been limited in scope and scale. This paper introduces new techniques that allow the application of PCE to be scaled up to larger DSP blocks with many noise sources, as needed for building blocks in software-defined radios (SDRs). Design space exploration algorithms that leverage the accuracy of PCE to estimate bit widths for fixed-point implementations of DSP blocks in an SDR system are explored, and their advantages will be presented.