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Power Profile Manipulation: A New Approach for...
Journal article

Power Profile Manipulation: A New Approach for Reducing Test Application Time Under Power Constraints

Abstract

This paper proposes a power profile manipulation approach which merges two distinct research directions in low power testing: minimization of test power dissipation and test application time reduction under power constraints. It is shown how complementary techniques can be easily combined through this approach to significantly increase test concurrency under power constraints. This is achieved in two steps: in the first step power dissipation …

Authors

Rosinger PM; Al-Hashimi BM; Nicolici N

Journal

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 10,

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publication Date

10 2002

DOI

10.1109/tcad.2002.802256

ISSN

0278-0070