Register-transfer level functional scan for hierarchical designs

This paper discusses the potential benefits of inserting scan chains (SCs) in hierarchical designs at the register-transfer level (RTL) of design abstraction. Using new algorithms for functional scan chain design, it is shown how tight timing constraints for design-for-test (DFT) planning at RTL can improve the performance of a circuit, when compared to its gate level counterpart, without any loss in testability.