In-System Constrained-Random Stimuli Generation for Post-Silicon Validation

When generating the verification stimuli in a pre-silicon environment, the primary objectives are to reduce the simulation time and the pattern count for achieving the target coverage goals. In a hardware environment, because an increase in the number of stimuli is inherently compensated by the advantage of real-time execution, the objective augments to considering hardware complexity when designing in-system stimuli generators that must operate according to user-programmable constraints. In this paper we introduce a structured methodology for porting in-system the constrained-random stimuli generation aspect from a presilicon verification environment.