A Generic Embedded Sequence Generator for Constrained-Random Validation with Weighted Distributions

Post-silicon validation is concerned for discovering design errors that escape to the silicon prototypes. Recent research efforts have shown how to reuse the constraints from presilicon verification to support post-silicon constrained-random validation. The objective is to subject the prototype to a large volume of random, yet functionally-compliant stimuli. In this paper, we present a new method that facilitates on-chip stimuli generation compliant to constraints with weighted distributions.