Journal article
A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding
Abstract
This paper details our experience of developing an MPEG-2 audio/video decoder which operates at main level/main profile, 720× 480 4:2:0 at 29.97 frames per second, with audio at 16 bits, 48 000 samples per second. The design has been developed with a focus on energy-efficiency.
Authors
Kinsman AB; Nicolici N
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 3, pp. 499–503
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
March 1, 2011
DOI
10.1109/tvlsi.2009.2034168
ISSN
1063-8210