Conference
Power Constrained Test Scheduling Using Power Profile Manipulation
Abstract
This paper presents a novel power profile manipulation technique which improves the test application time of existing power constrained test scheduling algorithms. This is achieved by test sequence reordering and rotation combined with a new power approximation model. Experiments using benchmark circuits show that use of this technique can lead to savings up to 25% in test time.
Authors
Rosinger PM; Al-Hashimi BM; Nicolici N
Volume
5
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
January 1, 2001
DOI
10.1109/iscas.2001.922032
Name of conference
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)