DFT infrastructure for broadside two-pattern test of core-based SOCs

Existing approaches for modular manufacturing test of core-based system-on-a-chip (SOC) devices do not provide any explicit mechanism for delivering two-pattern tests in the broadside mode, which is necessary to achieve reliable coverage of delay and stuck-open faults. Although wrapper input cells can be enhanced with two memory elements to address this problem, this incur a large test area overhead. This paper proposes a novel architecture for …