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On-Chip Constrained Random Stimuli Generation for...
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On-Chip Constrained Random Stimuli Generation for Post-Silicon Validation Using Compact Masks

Abstract

During post-silicon validation a large number of constrained random stimuli are applied to expose the subtle design errors that have escaped to the silicon prototypes. In this paper we present a new method to design constrained random stimuli generators, which are programmable and can be placed on-chip to generate extensive random, yet functionally-compliant, sequences for real-time/in-system validation. The basic idea is to translate the …

Authors

Shi X; Nicolici N

Pagination

pp. 1-10

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publication Date

October 1, 2014

DOI

10.1109/test.2014.7035337

Name of conference

2014 International Test Conference