Conference
A New Algorithm for Post-Silicon Clock Measurement and Tuning
Abstract
The number of speedpaths in modern high-performance designs is in the range of millions. Due to unmodelled electrical effects, such as process variations and systemic delay defects, the speedpaths are difficult to be measured accurately before the first silicon samples are available. To tolerate these unmodelled electrical effects, clock tuning elements are employed to aid the post-silicon clock measurement and tuning. In this paper we describe …
Authors
Lak Z; Nicolici N
Pagination
pp. 53-59
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
October 1, 2011
DOI
10.1109/dft.2011.14
Name of conference
2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems