Power constrained test scheduling using power profile manipulation

This paper presents a novel power profile manipulation technique which reduces the testing time of the recently proposed power constrained test scheduling algorithms. The power profile manipulation technique consists of reordering and rotating test sequences combined with a new power approximation model. The integration of the proposed power profile manipulation technique in power conscious test scheduling algorithms produced testing time savings of up to 25% for benchmark circuits synthesized in AMS 0.35 μn technology.