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Testability Trade-Offs for Bist Rtl Data Paths:...
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Testability Trade-Offs for Bist Rtl Data Paths: The Case for Three Dimensional Design Space

Abstract

Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper Focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation.

Authors

Nicolici N; Al-Hashimi BM

Pagination

pp. 802-809

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publication Date

January 1, 2001

DOI

10.1109/date.2001.915128

Name of conference

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001
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