subject area of
- A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation Academic Article
- A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning Academic Article
- A Pipeline Architecture for Processing of DNA Microarrays Images Academic Article
- A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding Academic Article
- A simple scheme for PSK demodulation Academic Article
- Addressing useless test data in core-based system-on-a-chip test Academic Article
- Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug Academic Article
- An Optimal and Practical Approach to Single Constant Multiplication Academic Article
- An Optimized Cell BE Special Function Library Generated by Coconut Academic Article
- Automated Range and Precision Bit-Width Allocation for Iterative Computations Academic Article
- Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test Academic Article
- Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation Academic Article
- Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment Academic Article
- BIST hardware synthesis for RTL data paths based on test compatibility classes Academic Article
- Bit-Flip Detection-Driven Selection of Trace Signals Academic Article
- Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory Academic Article
- Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types Academic Article
- Cooperative Token-Ring Scheduling For Input-Queued Switches Academic Article
- Correction to The Proof Of Theorem 2 In "parallel Signature Analysis Design With Bounds On Allasing" Academic Article
- Cryogenic operation of CMOS-based microsystems and computers Academic Article
- DFT infrastructure for broadside two-pattern test of core-based SOCs Academic Article
- Design principles for practical self-routing nonblocking switching networks with O(N·log N) bit-complexity Academic Article
- Design-for-Debug Architecture for Distributed Embedded Logic Analysis Academic Article
- Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison Academic Article
- Editorial: Silicon debug and diagnosis Academic Article
- Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation Academic Article
- Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation Academic Article
- Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation Academic Article
- Guest Editorial Academic Article
- Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research Academic Article
- IEEE Design and Test of Computers Journal
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Journal
- IEEE Transactions on Computers Journal
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems Journal
- IET Computers and Digital Techniques Journal
- Image compression using KLT, wavelets and an adaptive mixture of principal components model Academic Article
- Journal of Electronic Testing: Theory and Applications (JETTA) Journal
- Journal of Systems Architecture Journal
- Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology Journal of VLSI Signal Processing Journal of Signal Processing Systems Journal
- Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging Academic Article
- Microprocessors and Microsystems Journal
- Modular SOC testing with reduced wrapper count Conference Paper
- Modular and rapid testing of SOCs with unwrapped logic blocks Academic Article
- Modular array structure for non-restoring square root circuit Academic Article
- Multifrequency TAM design for hierarchical SOCs Conference Paper
- Multiple scan chains for power minimization during test application in sequential circuits Academic Article
- New RTD large-signal DC model suitable for PSPICE Academic Article
- NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging Academic Article
- Numerical Data Representations for FPGA-Based Scientific Computing Academic Article
- On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC Academic Article
- On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC Academic Article
- On Using Lossy Compression for Repeatable Experiments during Silicon Debug Academic Article
- On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging Academic Article
- On the Permutation Capability of Multistage Interconnection Networks Academic Article
- On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation Academic Article
- Power complexity of multiplexer-based optoelectronic crossbar switches Academic Article
- Power profile manipulation: a new approach for reducing test application time under power constraints Academic Article
- Power-conscious test synthesis and scheduling Academic Article
- Real-Time Lossless Compression for Silicon Debug Academic Article
- Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey Academic Article
- Scan Architecture With Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction Academic Article
- Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy Academic Article
- Selftuning control of some pilot plant processes Academic Article
- Special issue on Model Based Engineering for Embedded Systems Design Academic Article
- Synchronization overhead in SOC compressed test Academic Article
- Temperature Characteristics and Analysis of Monolithic Microwave CMOS Distributed Oscillators With ${G}_{m}$-Varied Gain Cells and Folded Coplanar Interconnects Academic Article
- Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains Conference Paper
- Testability Trade-Offs for BIST Data Paths Academic Article
- Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns Academic Article
- Time-Multiplexed Compressed Test of SOC Designs Academic Article
- Timestamp Temporal Logic (TTL) for Testing the Timing of Cyber-Physical Systems Academic Article
- Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses Academic Article
- Transactions on Embedded Computing Systems Journal
- Using horizontal prefetching to circumvent the jump problem Academic Article
- Variable-length input huffman coding for system-on-a-chip test Conference Paper
- Wrapper design for multifrequency IP cores Academic Article