publication venue for
- Fast Inner-Product Algorithms and Architectures for Deep Neural Network Accelerators. 73:495-509. 2024
- DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems. 72:1163-1177. 2023
- Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems. 70:2098-2111. 2021
- Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation. 65:1-1. 2016
- A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning. 63:1074-1084. 2014
- NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging. 62:524-535. 2013
- Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging. 61:1563-1575. 2012
- Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types. 60:1652-1663. 2011
- On Using Lossy Compression for Repeatable Experiments during Silicon Debug. 60:937-950. 2011
- Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses. 60:498-507. 2011
- An Optimized Cell BE Special Function Library Generated by Coconut. 58:1126-1138. 2009
- DFT infrastructure for broadside two-pattern test of core-based SOCs. 55:470-485. 2006
- Multiple scan chains for power minimization during test application in sequential circuits. 51:721-734. 2002
- Correction to The Proof Of Theorem 2 In "parallel Signature Analysis Design With Bounds On Allasing". 47:1426-1426. 1998
- Using horizontal prefetching to circumvent the jump problem. 40:1287-1291. 1991