publication venue for
- Thresholding Decision-Directed Descent (T3D): A Tuning Solution for DDR5 DRAM DFEs. 32. 2024
- Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks. 28:750-763. 2020
- Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation. 25:1866-1880. 2017
- Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. 20:1118-1131. 2012
- Design-for-Debug Architecture for Distributed Embedded Logic Analysis. 19:1380-1393. 2011
- Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation. 19:559-570. 2011
- A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding. 19:499-503. 2011
- Time-Multiplexed Compressed Test of SOC Designs. 18:1159-1172. 2010
- Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns. 17:1353-1357. 2009
- Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison. 14:537-548. 2006
- Modular and rapid testing of SOCs with unwrapped logic blocks. 13:1275-1285. 2005
- Wrapper design for multifrequency IP cores. 13:678-685. 2005
- Synchronization overhead in SOC compressed test. 13:140-152. 2005
- Guest editorial. 11:753-754. 2003