publication venue for
- Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems 2018
- Bit-flip Detection-Driven Selection of Trace Signals 2016
- Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains 2007
- Multifrequency TAM design for hierarchical SOCs 2006
- Modular SOC testing with reduced wrapper count 2005
- Variable-length input huffman coding for system-on-a-chip test 2003
- Bit-Flip Detection-Driven Selection of Trace Signals. 37:1076-1089. 2018
- MCXplore: Automating the Validation Process of DRAM Memory Controller Designs. 37:1-1. 2017
- On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation. 35:1012-1025. 2016
- Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation. 35:2118-2130. 2016
- On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging. 31:1845-1856. 2012
- An Optimal and Practical Approach to Single Constant Multiplication. 30:1373-1386. 2011
- Automated Range and Precision Bit-Width Allocation for Iterative Computations. 30:1265-1278. 2011
- Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory. 29:405-413. 2010
- Real-Time Lossless Compression for Silicon Debug. 28:1387-1400. 2009
- Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. 28:285-297. 2009
- Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug. 28:285-297. 2009
- Real-time lossless compression for silicon debug. 28:1387-1400. 2009
- Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. 27:2092-2097. 2008
- Scan Architecture With Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction. 23:1142-1153. 2004
- Addressing useless test data in core-based system-on-a-chip test. 22:1568-1580. 2003
- Power profile manipulation: a new approach for reducing test application time under power constraints. 21:1217-1225. 2002
- BIST hardware synthesis for RTL data paths based on test compatibility classes. 19:13751385. 2000
- BIST hardware synthesis for RTL data paths based on test compatibility classes. 19:1375-1385. 2000
- New RTD large-signal DC model suitable for PSPICE. 14:167-172. 1995