Journal article
Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems
Abstract
This article addresses the challenge of allowing simultaneous and predictable accesses to shared data on multi-core systems. We propose a collection of predictable cache coherence protocols, which mandate the use of certain design invariants to ensure predictability. In particular, we enforce these invariants by augmenting the classic modify-share-invalid (MSI) protocol and modify-exclusive-share-invalid (MESI) protocol. This allows us to …
Authors
Kaushik AM; Hassan M; Patel H
Journal
IEEE Transactions on Computers, Vol. 70, No. 12, pp. 2098–2111
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
10.1109/tc.2020.3037747
ISSN
0018-9340