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A Comparative Study of Predictable DRAM...
Journal article

A Comparative Study of Predictable DRAM Controllers

Abstract

Recently, the research community has introduced several predictable dynamic random-access memory (DRAM) controller designs that provide improved worst-case timing guarantees for real-time embedded systems. The proposed controllers significantly differ in terms of arbitration, configuration, and simulation environment, making it difficult to assess the contribution of each approach. To bridge this gap, this article provides the first comprehensive evaluation of state-of-the-art predictable DRAM controllers. We propose a categorization of available controllers, and introduce an analytical performance model based on worst-case latency. We then conduct an extensive evaluation for all state-of-the-art controllers based on a common simulation platform, and discuss findings and recommendations.

Authors

Guo D; Hassan M; Pellizzoni R; Patel H

Journal

ACM Transactions on Embedded Computing Systems, Vol. 17, No. 2, pp. 1–23

Publisher

Association for Computing Machinery (ACM)

Publication Date

March 31, 2018

DOI

10.1145/3158208

ISSN

1539-9087

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