subject area of
- A Comparative Study of Predictable DRAM Controllers Journal Articles
- A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation Journal Articles
- A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning Journal Articles
- A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding Journal Articles
- Addressing useless test data in core-based system-on-a-chip test Journal Articles
- Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug Journal Articles
- Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug Journal Articles
- An Optimal and Practical Approach to Single Constant Multiplication Journal Articles
- An Optimized Cell BE Special Function Library Generated by Coconut Journal Articles
- Analysing trade-offs in scan power and test data compression for systems-on-a-chip Journal Articles
- Analysis of a linearly constrained least squares algorithm for adaptive beamforming Journal Articles
- Automated Range and Precision Bit-Width Allocation for Iterative Computations Journal Articles
- Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test Journal Articles
- Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation Journal Articles
- Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment Journal Articles
- BIST hardware synthesis for RTL data paths based on test compatibility classes Journal Articles
- BIST hardware synthesis for RTL data paths based on test compatibility classes Journal Articles
- Bit-Flip Detection-Driven Selection of Trace Signals Journal Articles
- Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory Journal Articles
- Bit-flip Detection-Driven Selection of Trace Signals Conferences
- Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems Conferences
- Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types Journal Articles
- Correction to The Proof Of Theorem 2 In "parallel Signature Analysis Design With Bounds On Allasing" Journal Articles
- Cryogenic operation of CMOS-based microsystems and computers Journal Articles
- DFT infrastructure for broadside two-pattern test of core-based SOCs Journal Articles
- DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems Journal Articles
- Design-for-Debug Architecture for Distributed Embedded Logic Analysis Journal Articles
- Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems Journal Articles
- Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison Journal Articles
- Dual multiple-polynomial LFSR for low-power mixed-mode BIST Journal Articles
- Editorial: Silicon debug and diagnosis Journal Articles
- Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation Journal Articles
- Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation Journal Articles
- Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis Journal Articles
- Fast Inner-Product Algorithms and Architectures for Deep Neural Network Accelerators Journal Articles
- Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation Journal Articles
- Guest editorial Journal Articles
- IEEE Micro Journal
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Journal
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems Journal
- IEEE transactions on computers Journal
- IET Computers and Digital Techniques Journal
- Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks Journal Articles
- Integration, the VLSI Journal Journal
- MCXplore: Automating the Validation Process of DRAM Memory Controller Designs Journal Articles
- Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging Journal Articles
- Microprocessors and Microsystems Journal
- Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing Journal Articles
- Minimising power dissipation in partial scan sequential circuits Journal Articles
- Modular SOC testing with reduced wrapper count Conferences
- Modular and rapid testing of SOCs with unwrapped logic blocks Journal Articles
- Multifrequency TAM design for hierarchical SOCs Conferences
- Multiple scan chains for power minimization during test application in sequential circuits Journal Articles
- New RTD large-signal DC model suitable for PSPICE Journal Articles
- NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging Journal Articles
- On Using Lossy Compression for Repeatable Experiments during Silicon Debug Journal Articles
- On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging Journal Articles
- On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation Journal Articles
- PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems Journal Articles
- PMC Journal Articles
- Power profile manipulation: a new approach for reducing test application time under power constraints Journal Articles
- RESEARCH AGENDA: SPACETIME COMPUTATION AND THE NEOCORTEX Journal Articles
- Real-Time Lossless Compression for Silicon Debug Journal Articles
- Real-time lossless compression for silicon debug Journal Articles
- Resource-constrained system-on-a-chip test: a survey Journal Articles
- Scan Architecture With Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction Journal Articles
- Selftuning control of some pilot plant processes Journal Articles
- Synchronization overhead in SOC compressed test Journal Articles
- Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains Conferences
- Thresholding Decision-Directed Descent (T3D): A Tuning Solution for DDR5 DRAM DFEs Journal Articles
- Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns Journal Articles
- Time-Multiplexed Compressed Test of SOC Designs Journal Articles
- Timestamp Temporal Logic (TTL) for Testing the Timing of Cyber-Physical Systems Journal Articles
- Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses Journal Articles
- Transactions on Embedded Computing Systems Journal
- Using horizontal prefetching to circumvent the jump problem Journal Articles
- Variable-length input huffman coding for system-on-a-chip test Conferences
- Wrapper design for multifrequency IP cores Journal Articles