publication venue for
- SALVO process for sub-50 nm low-V/sub T/ replacement gate CMOS with KrF lithography 2000
- 50 nm Vertical Replacement-Gate (VRG) pMOSFETs 2000
- The ballistic nano-transistor 1999
- An effective gate resistance model for CMOS RF and noise modeling 1998
- Progress toward 10 nm CMOS devices 1998
- Two-dimensional dopant profiling of a 60 nm gate length nMOSFET using scanning capacitance microscopy 1998
- Ultra-thin gate oxides and ultra-shallow junctions for high performance, sub-100 nm pMOSFETs 1998
- Junction delineation of 0.15 μm MOS devices using scanning capacitance microscopy 1997
- Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs 1997
- Modelling of breakdown voltage and its temperature dependence in SAGCM InP/InGaAs avalanche photodiodes 1994
- A new charge pumping method for determining the spatial interface state density distribution in MOSFETs 1990
- Subsurface junction field effect transistor (SJFET) 1980