SALVO process for sub-50 nm low-V/sub T/ replacement gate CMOS with KrF lithography

We present the SALVO CMOS process, first device data and simulation study with the following features: (1) self-aligned local channel implants for SCE reduction; (2) sub-50 nm fabrication using only current production tools; (3) replacement gate with dual-polysilicon for low V/sub T/; (4) low aspect-ratio gates with CD insensitive to lithography and etch profile variability. The first demonstration of SALVO process shows it is a viable candidate for future ULSI CMOS production, in view of its versatility, controllability and compatibility.