publication venue for
- On-chip constrained random stimuli generation for post-silicon validation using compact masks 2014
- In-system constrained-random stimuli generation for post-silicon validation 2012
- Automated trace signals selection using the RTL descriptions 2010
- Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs 2008
- On using lossless compression of debug data in embedded logic analysis 2007
- On concurrent test of wrapped cores and unwrapped logic blocks in SOCs 2005
- Time/area tradeoffs in testing hierarchical SOCs with hard mega-cores 2004
- On reducing wrapper boundary register cells in modular soc testing 2003
- Integrated test data decompression and core wrapper design for low-cost system-on-a-chip testing 2002
- Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation 2001
- Power conscious test synthesis and scheduling for BIST RTL data paths 2000