A Framework for Explainable, Comprehensive, and Customizable Memory-Centric Workloads
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abstract
Modern computer applications process massive volumes of data from sensors and cameras, putting tremendous demands on the system's memory bandwidth, energy, and predictability. Because main memory is the main bottleneck in such computing systems, researchers have proposed a number of novel memory solutions. However, because memory-centric benchmarks have been slow to emerge, these solutions are assessed using CPU-centric benchmarks or high-level memory access patterns benchmarks such as sequential vs random or read vs write. As a result, we present RAMify, a user-friendly and highly flexible framework for creating memory-centric architecture-aware workloads.
In this thesis, RAMify is presented, and its architecture, key features, and how to use it to formulate new performance benchmarks for evaluating memory subsystems are discussed. I also discuss how to update the framework for software development, and highlight the need for memory-centric benchmarks as well as the importance of RAMify in evaluating memory systems in modern computing platforms. We generate 132 workloads from RAMify to compare them with SPEC-CPU2006 and MemBen workloads. Furthermore, we utilized these workloads to perform a comparative study between the High Bandwidth memory (HBM) and Double Data Rate generation 4 (DDR4). Finally, we investigate HBM through the perspective of real-time systems, focusing on the HBM device to capture architectural factors that influence timing predictability, such as device access behaviour, timing characteristics, and performance measures.
