publication venue for
- Duetto: Latency Guarantees at Minimal Performance Cost 2021
- Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence 2021
- A Methodology for Automated Design of Embedded Bit-flips Detectors in Post-Silicon Validation 2015
- Automated data analysis solutions to silicon debug 2009
- Finite Precision bit-width allocation using SAT-Modulo Theory 2009
- Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation 2008
- On Automated Trigger Event Generation in Post-Silicon Validation 2008
- Automated trace signals identification and state restoration for improving observability in post-silicon validation 2008
- On automated trigger event generation in post-silicon validation 2008
- Low Cost Debug Architecture using Lossy Compression for Silicon Debug 2007
- Delay fault testing of core-based systems-on-a-chip 2003
- Test data compression: the system integrator's perspective 2003
- Detecting state coding conflicts in STGs using integer programming 2002
- Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression 2002
- Testability trade-offs for BIST RTL data paths: the case for three dimensional design space 2001
- Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits 2000
- Efficient BIST hardware insertion with low test application time for synthesized data paths 1999