publication venue for
- The performance of hypermesh NoCs in FPGAs 2012
- Combined optimal and heuristic approaches for multiple constant multiplication 2010
- Computational bit-width allocation for operations in vector calculus 2009
- RTL Scan Design for Skewed-Load At-Speed Test under Power Constraints 2006
- Compressed embedded diagnosis of logic cores 2004
- Functional illinois scan design at RTL 2004
- Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding 2002