Wafer level and chip size direct wafer bonding at room temperature

Wafer level (Si, LiNbO3, and LiTaO3) and chip size (GaAs, GaP, and InAs) wafers were directly bonded after cleaning by using low energy Ar-ion and Ar fast atom beam (Ar-FAB) sources, respectively at room temperature. The interface quality of both the wafer level and chip size samples was investigated by tensile pulling test, current-voltage measurements, and transmission electron microscopy (TEM). Tensile test showed strong bonding strength comparable to bulk materials in both cases. Atomic level bonding associated with poor visibility due to crystal misorientation was observed in the Si/GaP and GaAs/GaP interfaces, whereas an amorphous layer of 3 nm was found in the Si/LiNbO3 interface. The estimated ideality factor was nearly unity and the non-leakage current in GaAs/GaP might be due to the absence of accumulated bubble like nano-regions across the interface. Bonding mechanism and potential of SAB processed wafer level and chip size bonded interfaces were discussed for the application optolectronics and MEMS devices.