Conference
A 330 MHz 4-way superscalar microprocessor
Abstract
This is a second-generation, highly-integrated superscalar processor implementing the Sparc V9 64b architecture. Performance is improved by increasing clock frequency and by improvements in the memory system. Clock rates up to 330 MHz are achieved. Microarchitecture improvements include a pre-fetch instruction, multiple outstanding block loads and stores, and support for a wide range of cache sizes and system frequencies. These result in …
Authors
Greenhill D; Anderson E; Bauman J; Charnas A; Cheerla R; Chen H; Doreswamy M; Ferolito P; Gopaladhine S; Ho K
Pagination
pp. 166-167
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
January 1, 1997
DOI
10.1109/isscc.1997.585318
Name of conference
1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers
Conference proceedings
2012 IEEE International Solid-State Circuits Conference
ISSN
0193-6530