The Development of Bipolar Log Domain Filters in a Standard CMOS Process

A design technique for implementing bipolar log domain filters in standard CMOS technology is proposed. The filters are constructed using lateral bipolar transistors and strongly-inverted MOSFET transistors. This paper presents a simple, SPICE compatible model for a lateral PNP transistor fabricated in 0.35µ CMOS, and demonstrates that this device can be used to map bipolar circuit designs into a CMOS process. Simulations of a biquadratic low pass filter indicate that cutoff frequencies of over 10 MHz and dynamic ranges on the order of 50 dB can be achieved. Experimental measurements from a prototype filter demonstrate the feasibility of the approach.