Home
Scholarly Works
A High-Throughput Maximum <i>a posteriori</i>...
Conference

A High-Throughput Maximum a posteriori Probability Detector

Abstract

This paper presents a maximum a posteriori probability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and, with Turbo decoding, can approach performance close to the channel capacity limit. The proposed detector utilizes a deep-pipelined architecture implemented in skew-tolerant domino and experimentally measured results verify the detector can achieve throughputs greater than 750MHz while consuming 2.4W. The detector is implemented in a 0.13μm CMOS technology and has a die area of 9.9 mm2.

Authors

Ratnayake R; Kavcic A; Wei G-Y

Pagination

pp. 455-458

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publication Date

September 1, 2007

DOI

10.1109/cicc.2007.4405772

Name of conference

2007 IEEE Custom Integrated Circuits Conference

Conference proceedings

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

ISSN

0886-5930
View published work (Non-McMaster Users)

Contact the Experts team