Parameter extraction and modelling of short-channel LDD MOSFETs for VLSI applications

We report on the effects of temperature and biasing voltages on the parasitic resistance (R/sub p/) and channel length reduction (/spl Delta/L) parameters in short-channel lightly-doped drain (LDD) NMOS transistors. These two parameters and their variation with operating conditions are required for the accurate modelling of MOS devices for VLSI applications. The results show that both R/sub p/ and /spl Delta/L vary with all operating bias voltages (drain, gate and substrate), and also with temperature. Using the extracted device parameters, current-voltage characteristics are simulated with SPICE and good agreement to experimental data is obtained. If the variations of these device parameters with operating conditions are not taken into account, the agreement is poor. Full details of the parameter extraction procedure and experimental results are described and discussed.<>