Conference
Index Mapping for Bit-Error Resilient Multiple Description Lattice Vector Quantizer
Abstract
This work addresses the construction of bit-error resilient multiple description lattice vector quantizers (MDLVQ) by proposing the design of a structured mapping $\gamma$ of side lattice points to binary indexes. We assume that the first description is correct while the second description may carry bit errors. To design the mapping $\gamma$ the set of side lattice points is first partitioned into Voronoi regions of an appropriate coarse …
Authors
Dumitrescu S; Chen Y; Chen J
Pagination
pp. 2588-2592
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
June 1, 2017
DOI
10.1109/isit.2017.8006997
Name of conference
2017 IEEE International Symposium on Information Theory (ISIT)