Conference
A Generic Embedded Sequence Generator for Constrained-Random Validation with Weighted Distributions
Abstract
Post-silicon validation is concerned for discovering design errors that escape to the silicon prototypes. Recent research efforts have shown how to reuse the constraints from presilicon verification to support post-silicon constrained-random validation. The objective is to subject the prototype to a large volume of random, yet functionally-compliant stimuli. In this paper, we present a new method that facilitates on-chip stimuli generation …
Authors
Shi X; Nicolici N
Pagination
pp. 57-62
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
July 1, 2017
DOI
10.1109/iolts.2017.8046199
Name of conference
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)