Progress toward 10 nm CMOS devices

One of the primary means for improving performance and increasing the scale of integration on a chip is the miniaturization of the electronic devices that comprise it. The SIA roadmap projects that future gains in performance will continue to accrue from this approach. One of the guiding principles for miniaturization has been the scaling of successful existing device designs to smaller dimensions. While there may be no compelling reason why the SIA targets cannot be achieved by continued scaling, an accurate assessment of the limiting performance that can be derived from conventional CMOS is crucial for identifying the principal impediments and for developing alternatives. Here, we identify five impediments that we have encountered as we attempt to scale CMOS technology toward 10 nm gate lengths: optical lithography, gate oxide tunneling, enhanced boron diffusion in the ultra-shallow junction, drive current saturation with decreasing oxide thickness, and the subthreshold current.