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Ultra-thin gate oxides and ultra-shallow junctions for high performance, sub-100 nm pMOSFETs

Abstract

Reports measurements of the DC characteristics of sub-100nm pMOSFETs that employ low leakage, ultra-thin gate oxides only 1-2nm thick and ultra-shallow junctions to achieve high current drive capability and transconductance. We demonstrate that I/sub Dsct/=0.23mA//spl mu/m can be achieved with a L/sub x/=65nm physical gate length at 15V using a 1.5nm gate oxide with a gate leakage current less than 20nA//spl mu/m/sup 2/ on devices without silicided contacts. But more importantly, we find no evidence of boron penetration through SiO/sub 2/ gate oxides as thin as 1.3nm, grown at 1000C using rapid thermal oxidation (RTO). Furthermore, for the first time, we have directly imaged the ultra-shallow p-n junctions that comprise a sub-100nm pMOSFET with an effective channel length of 20nm to show that the lateral extent of the junction is approximately half that of the vertical junction depth. We surmise that the enhanced vertical diffusion has an adverse effect on subthreshold characteristic of sub-100nm pMOSFETs.

Authors

Timp G; Agarwal A; Bourdella KK; Bower J; Boone T; Ghetti A; Green M; Gamo J; Gossmann H; Jacobson D

Pagination

pp. 1041-1043

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publication Date

January 1, 1998

DOI

10.1109/iedm.1998.746534

Name of conference

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

Conference proceedings

International Electron Devices Meeting 1998 Technical Digest (Cat No98CH36217)

ISSN

0163-1918

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