Conference
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT
Abstract
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is deriving equations for logic gates implementing each output signal of the circuit. This is usually done using reachability graphs. In this paper, we avoid constructing the reachability graph of …
Authors
Khomenko V; Koutny M; Yakovlev A
Pagination
pp. 1-10
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
January 1, 2004
DOI
10.1109/csd.2004.1309112
Name of conference
Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004.