Conference
Power conscious test synthesis and scheduling for BIST RTL data paths
Abstract
Previous research has outlined that power dissipated during test application is substantially higher than during functional operation, which leads to loss of yield and decreases reliability. This paper shows for the first time how power is minimized in BIST RTL data paths by using power conscious test synthesis and test scheduling. According to the necessity for achieving the required test efficiency, power dissipation is classified into …
Authors
Nicolici N; Al-Hashimi BM
Pagination
pp. 662-671
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
January 1, 2000
DOI
10.1109/test.2000.894261
Name of conference
Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)
Conference proceedings
International Test Conference 1999 Proceedings (IEEE Cat No99CH37034)
ISSN
1089-3539