Power-constrained embedded memory BIST architecture

A new flexible, hierarchical and distributed power-constrained embedded memory built-in self-test (BIST) architecture for complex and heterogeneous systems-on-a-chip (SOCs) is presented. The proposed architecture consists of a shared technology-independent BIST controller, low area and low power memory BIST wrappers and serial interconnect between them for low routing-overhead. Due to its flexibility, in addition to reducing routing complexity and achieving high test concurrency under power constraints, the presented solution can simultaneously support multiple test algorithms for heterogeneous memories, as well as embed custom test algorithms required for new memory faults.