Delay Fault Testing of Core-Based Systems-on-a-Chip

Existing approaches for modular manufacturing testing of core-based systems-on-a-chip (SOCs) do not provide any explicit mechanism for high quality two-pattern tests required for performance validation through delay fault testing. This paper proposes a new approach for broadside delay fault testing of core-based SOCs by adapting the existing solutions for automatic test pattern generation and design for test support, test access mechanism division and test scheduling.