Conference
Hardware/Software Co-testing of Embedded Memories in Complex SOCs
Abstract
A novel approach for testing embedded memories in complex systems-on-a–chip (SOCs) is presented. The proposed solution aims to balance the usage of the existing on-chip resources and dedicated design for test (DFT) hardware such that the functional power constraints are not exceeded during test while trading-off the testing time against DFT area and performance overhead. The suitability of software-centric and hardware-centric approaches for …
Authors
Fang BH; Xu Q; Nicolici N
Pagination
pp. 599-605
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
January 1, 2003
DOI
10.1109/iccad.2003.1257872
Name of conference
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)