Satisfiability-Based Analysis of Failing Traces During Post-Silicon Debug

Since integrating memory blocks on-chip became affordable, embedded logic analysis has been employed during post-silicon validation and debugging. Failing traces obtained through embedded logic analysis can be used to understand functional design errors, a problem that has been studied extensively over the past decade. In this paper, we show that post-processing failing traces using a computational approach, based on Boolean satisfiability, can aid also the identification of electrically-induced design errors, e.g., bit-flips.