Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation

The constrained-random methodology is widely used during the pre-silicon verification of very-large scale integrated circuits. Recently, research efforts have been made to support the application of constrained-random patterns during the post-silicon validation stage. In this paper, we present a new method, including both software algorithms and on-chip hardware structures, for in-system constrained-random generation of stimuli sequences that …