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On Supporting Sequential Constraints for On-Chip...
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On Supporting Sequential Constraints for On-Chip Generation of Post-Silicon Validation Stimuli

Abstract

Post-silicon validation plays a critical role in exposing design errors in early silicon prototypes. Its effectiveness is conditioned by in-system application of functionally-compliant stimuli for extensive periods of time. This is achieved by expanding on-the-fly randomized functional sequences, which are subjected to user-programmable constraints. In this paper we present a method to extend the existing work for on-chip generation of …

Authors

Shi X; Nicolici N

Pagination

pp. 107-112

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publication Date

November 1, 2014

DOI

10.1109/ats.2014.30

Name of conference

2014 IEEE 23rd Asian Test Symposium