Conference
Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores with Multiple Clock Domains
Abstract
Even though many embedded cores contain several clock domains, most published methods for wrapper design have been limited to single-frequency cores. Cumbersome and invasive design techniques, such as insertion of test points, are needed to make these methods applicable to current-generation embedded cores. This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. The proposed 1500-compliant …
Authors
Xu Q; Nicolici N; Chakrabarty K
Volume
26
Pagination
pp. 1539-1547
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
August 1, 2007
DOI
10.1109/tcad.2007.893556
Conference proceedings
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue
8
ISSN
0278-0070