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Minimisation of power dissipation during test...
Journal article

Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing

Authors

Nicolici N; Al-Hashimi BM; Williams AC

Journal

IET Computers & Digital Techniques, Vol. 147, No. 5,

Publisher

Institution of Engineering and Technology (IET)

Publication Date

January 1, 2000

DOI

10.1049/ip-cdt:20000537

ISSN

1751-8601

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