RTL Scan Design for Skewed-Load At-Speed Test under Power Constraints

This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for power-constrained at-speed testing. By analyzing a circuit at the RTL, where design complexity is lower than at the gate netlist level, one can divide a circuit into multiple partitions, which can be tested independently in order to reduce test power. Despite activating one partition at a time, we show how through conscious construction of …