Conference
On Bypassing Blocking Bugs during Post-Silicon Validation
Abstract
Design errors (or bugs) inadvertently escape the pre silicon verification process. Before committing to a re-spin, it is expected that the escaped bugs have been identified during post-silicon validation. This is however hindered by the presence of blocking bugs in one erroneous module that inhibit the search for bugs in other parts of the chip that process data received from the erroneous module. In this paper we discuss how to design a novel …
Authors
Daoud EA; Nicolici N
Pagination
pp. 69-74
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
May 1, 2008
DOI
10.1109/ets.2008.29
Name of conference
2008 13th European Test Symposium